In recent years, many applications have been found for the integration of OLED with standard CMOS circuits, for example in near-to-eye lenses. The integration of OLED and CMOS into the same chip can provide many benefits, such as compact size, fast speed, low power consumption etc.
In a typical OLED on MOS structure for use as a display, a wafer (e.g. a silicon wafer) having an integrated circuit is provided. Metal pixels are photolithographically patterned on top of the wafer to serve as electrodes of the OLED and so as to form a reflective layer for reflecting the light from the OLED. An organic compound layer is then formed on top, covering the metal pixels as well as the gap(s) between the metal pixels.
However, the present inventors have appreciated that problems may arise since the standard CMOS process is not well suited to the integration of OLED on CMOS, for at least two reasons. Firstly, it is common to produce top metals with a certain roughness in a standard CMOS process. The root mean square of the roughness of the top metal produced in a standard CMOS process is commonly more than 5 nanometers. This is because a very smooth surface such as less than 3 nanometers is not required in the standard CMOS. But the rough surface of the top metal tends to lead to high leakage of the OLED devices. It is believed that non-standard processes could solve this problem. However, semiconductor foundries are generally reluctant to develop non-standard processes due to high development and production costs. Moreover, a typical Physical Vapor Deposition (PVD) tool is not purposely designed to produce metal with a very smooth surface. Secondly, the thickness of metals normally used in CMOS processes is about 8000 Å (800 nm) resulting in a pixel gap of comparable depth. OLED organic materials deposited in the pixel gap(s) can induce side wall emitting and high electrical fields at the metal edge. As a result, both the efficiency and reliability of the OLED device is degraded. To solve these problems, in the standard CMOS process, the pixel gap(s) is/are filled by insulating dielectric materials.
The inventors have found that a plasma etching process can be employed to remove the insulating materials from the top surface of the pixel electrodes. However, this results in increased complexity and additional cost. Moreover, there is the risk that the pixel metal surface may suffer plasma etching damage, resulting in increased roughness of the pixel electrode surface.
The inventors have appreciated that alternatively it is possible to employ non standard CMOS processes such as Chemical Vapor Deposition (CVD) to fill the pixel gap(s), chemical mechanical polishing to flatten the topology and etching back to remove any insulation materials from the top surface of the pixel electrodes. However, these non-standard CMOS processes will increase the production costs.